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Freescale Semiconductor /MKL28T7_CORE1 /SCG /SOSCCSR

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Interpret as SOSCCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SOSCEN 0 (0)SOSCSTEN 0 (0)SOSCLPEN 0 (0)SOSCERCLKEN 0 (0)SOSCCM 0 (0)SOSCCMRE 0 (0)LK 0 (0)SOSCVLD 0 (0)SOSCSEL 0 (0)SOSCERR

SOSCCM=0, SOSCSEL=0, LK=0, SOSCERR=0, SOSCLPEN=0, SOSCEN=0, SOSCSTEN=0, SOSCERCLKEN=0, SOSCVLD=0, SOSCCMRE=0

Description

System OSC Control Status Register

Fields

SOSCEN

System OSC Enable

0 (0): System OSC is disabled

1 (1): System OSC is enabled
SOSCSTEN

System OSC Stop Enable

0 (0): System OSC is disabled in Stop modes

1 (1): System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1.
SOSCLPEN

System OSC Low Power Enable

0 (0): System OSC is disabled in VLP modes

1 (1): System OSC is enabled in VLP modes
SOSCERCLKEN

System OSC 3V ERCLK Enable

0 (0): System OSC 3V ERCLK output clock is disabled.

1 (1): System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled.
SOSCCM

System OSC Clock Monitor

0 (0): System OSC Clock Monitor is disabled

1 (1): System OSC Clock Monitor is enabled
SOSCCMRE

System OSC Clock Monitor Reset Enable

0 (0): Clock Monitor generates interrupt when error detected

1 (1): Clock Monitor generates reset when error detected
LK

Lock Register

0 (0): This Control Status Register can be written.

1 (1): This Control Status Register cannot be written.
SOSCVLD

System OSC Valid

0 (0): System OSC is not enabled or clock is not valid

1 (1): System OSC is enabled and output clock is valid
SOSCSEL

System OSC Selected

0 (0): System OSC is not the system clock source

1 (1): System OSC is the system clock source
SOSCERR

System OSC Clock Error

0 (0): System OSC Clock Monitor is disabled or has not detected an error

1 (1): System OSC Clock Monitor is enabled and detected an error

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data